1. Field of the Invention
The invention relates to the field of computer architecture, specifically the selection of signals within the computer for use by peripheral component interconnect (PCI) devices and associated controllers.
2. Description of Related Technology
Peripheral component interconnect (PCI) technology is well known within the computer industry. Generally, PCI refers to a local or processor-independent bus standard. The PCI architecture generally utilizes a bridge to couple the main processor to a PCI bus used to interface with a variety of possible peripheral components. As used herein, the term xe2x80x9cperipheral componentxe2x80x9d refers not only to a discrete computer peripheral component (such as a mass storage, input/output, or network interface device), but also to any related or ancillary components, such as circuit boards, associated therewith. The PCI architecture utilizes an external bus of finite width (such as 32 or 64 bits) operating at a given frequency (such as 33 or 66 MHz) which is used to carry both address information and write/read data to and from so-called PCI slots typically located on the computer motherboard. Hence, address information and data is multiplexed onto the PCI bus as determined by a clock circuit. The PCI architecture also includes a xe2x80x9cburstxe2x80x9d mode, which allows the transfer of discrete amounts of data with only one address transfer operation. The PCI bridge has the unique characteristic of being able to independently form burst access operations. Specifically, the PCI bridge can independently recognize the addressing scheme of individual transfers, and form those in a given sequence into a burst transmission. This approach is meant to accelerate bus operations, thereby increasing the PCI bus bandwidth.
Inherent in the operation of the PCI architecture is the proper selection of the clock signal frequency applied to a given PCI slot by the computer""s internal clock circuit. In most applications, this clock signal must match that internal clock frequency of the peripheral component received within the slot. Prior art computer systems can generally be grouped into one of three types: (i) those having PCI slots and clock circuits using only one clock frequency; (ii) those having PCI slots and clock circuits using multiple frequencies which can not be selected automatically; or (iii) those utilizing multiple available clock frequencies which are automatically selected by a programmable logic device such as a programmable array logic (PAL) or grouped array logic (GAL) device. The limitations of the first group of systems are readily apparent, since only those components having a single given clock frequency can be accommodated. The more advanced systems of the second group have the ability to accommodate peripheral components of varying internal clock frequency; however, such systems require operator action or programming to configure the PCI slot to be supplied with a signal having a frequency matching that of the peripheral component""s internal clock. The third group of systems represent an improvement over the first and second groups in that they are capable of automatically recognizing the internal clock frequency of a peripheral component when it is plugged into a given PCI slot, and providing a clock signal of the desired frequency to that slot. FIG. 1 illustrates one such prior art clock circuit capable of automatic frequency selection.
The circuit of FIG. 1 utilizes two clock generators 10, 20 to generate the clock signals input to the GAL/PAL clock driver 40. The output of the driver 40 is input to a PCI controller 60 as well as the PCI slots 50. A signal from the PCI slots 50 (M66EN in FIG. 1) is input to the clock driver 40 to select the appropriate frequency output from the driver 40. A third clock generator 30 is used to generate one or more frequencies needed within other portions of the design but not generated by the other clock generators 10, 20.
However, prior art systems such as that shown in FIG. 1 suffer from certain disabilities relating to the use of programmable logic to generate and select the appropriate signal frequency. Specifically, the array logic necessarily includes finite propagation delays which can result in variable output signal timing relationships. If a propagation delay is introduced into the transmission path of a given clock signal, that signal will be out of phase (or at least have an unknown phase relationship) with respect to other clock signals of the same frequency. Such propagation delays may ultimately result in control and/or data transfer violations within the system.
Furthermore, the aforementioned prior art array logic does not maintain a constant phase relationship between the input and output of the clock driver. If the computer""s PCI architecture is completely synchronous, all the relevant components (such as Northbridge controller(s), PCI slots, NIC, Video) on the PCI bus generally must perform transactions on the rising-edge of the clock events. If there is a phase difference between the clocks providing input to the clock driver and the output signal of the clock driver, such a difference will have an effect either on the setup or hold times associated with the aforementioned components, depending on a positive or negative phase difference between clock signals provided to the different devices.
Additionally, the cost and effort associated with implementing a GAL/PAL-based device in computer applications is significant, thereby increasing the cost of the personal computer or other device in which the circuit is ultimately incorporated. Personal computers and other personal electronic devices are characteristically xe2x80x9clow marginxe2x80x9d products; hence, even small reductions in the cost of manufacturing can be significant in terms of the profitability and competitiveness of a given product.
Based on the foregoing, an improved clock circuit and method of generating a clock signal are needed which allow the automatic selection and provision of a clock signal appropriate for the peripheral component inserted within a given PCI slot. Specifically, such an improved circuit and method would automatically determine the internal operating frequency of the peripheral component when the component was plugged into the PCI slot, select the clock signal having the same frequency as, or having a predetermined relationship to, that of the peripheral component from a plurality of possible frequencies, and provide a clock signal with a matching frequency, or bearing some desired relationship to the clock signal of the peripheral component, back to the peripheral component and any other component related thereto. The construction of such a circuit would ideally be both simple and cost effective to implement, thereby allowing for increased host computer reliability and reduced manufacturing cost for the circuit and computer as a whole. Furthermore, such an improved circuit would also make negligible (or constant) the signal propagation delay through the clock driver, and maintain a constant phase relationship between the clock signals that are input to and output from the driver. Lastly, the design of such a circuit would ideally be such so as to permit scaling of the output so that varying clock frequencies could be readily accommodated using a given reference clock generator.
The present invention satisfies the aforementioned needs by providing an improved apparatus and method for automatically selecting the appropriate signal from a plurality of possible signals based on the configuration of a peripheral component installed within a computing device.
In a first aspect of the invention, an improved clock circuit is disclosed which is capable of simply, automatically, and reliably selecting the appropriate clock frequency of a signal which is supplied to a peripheral component. In one embodiment, a plurality of clock signals are generated by a reference clock generator and input to a phase locked loop (PLL), which is used as a clock driver. From these clock signals, the PLL selects the clock signal having the same frequency as that of the internal clock of the peripheral component, and outputs this signal to the peripheral component. Selection of the clock signal is based on a M66EN signal generated by the PCI slot, and associated PCI bus, which receives the peripheral component, when the component is plugged into the slot.
In a second aspect of the invention, an improved scalable clock circuit is disclosed. In addition to the use of the PLL as described above, a feedback circuit is used in conjunction with the PLL to generate frequencies in addition to those generated by the reference generator and supplied to the PCI slot. In one embodiment, a multiplier circuit is used in the feedback loop of the PLL in order to generate frequencies which are integer multiples of the frequencies generated by the reference signal generator. With this arrangement, the clock circuit can generate both those frequencies required by the PCI slot (such as 33 and 66 MHz), as well as integer multiples of these frequencies which may be needed by other components of the system, without having to employ a second reference generator.
In a third aspect of the invention, a computing device and circuit board incorporating the aforementioned clock circuit is disclosed. In one embodiment, the computing device is a personal computer having a motherboard with one or more PCI slots capable of receiving peripheral components with differing internal operating clock frequencies. The clock circuit of the present invention permits the automatic selection of the appropriate clock signal for the component plugged into the slot, thereby facilitating the change-out of peripheral components within the computer by the operator with minimum effort. The clock signal selected and output by the clock driver is also input to a Northbridge controller which, inter alia, controls the operation of the PCI slot(s) and bus.
In a fourth aspect of the invention, an improved method for automatically selecting and configuring the parameter(s) of a signal, and providing the signal to a peripheral component, is disclosed. A plurality of signals having different values for the parameter(s) of interest are first generated. Another signal relating to the configuration of the peripheral component is also generated; this latter signal is used to control the selection of the appropriate signal from the aforementioned plurality for use with the peripheral component. In one embodiment, two clock signals having different frequencies are generated by a clock generator within a personal computer. These clock signals are input to a phase locked loop clock driver, which matches its output signal frequency to that of the internal clock of the peripheral component based on the aforementioned configuration. The xe2x80x9cmatchedxe2x80x9d output clock signal is provided to the peripheral component and other components, such as the aforementioned PCI controller, if desired.
These and other features of the invention will become more fully apparent from the following description and appended claims taken in conjunction with the following drawings.